1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing thereof. Particularly, the present invention relates to a structure of an insulating gate type thyristor.
2. Description of the Background Art
In a general, low switching loss, low on-state voltage, high speed operation and high controllable current are required in switching device.
Switching loss refers to the power loss generated when a switching element is set to a conductive state (referred to as "turn-on" hereinafter), or to a cut off state (referred to as "turn-off" hereinafter). Steady-state loss refers to the power loss represented by the product of a forward voltage drop generated by on-resistance in a steady state after being turned on (referred to as "on-state" hereinafter) and the conducting current. Controllable current is defined as the maximum main current that can be turned off.
An insulating gate type thyristor is known as a switching element satisfying these demands. An insulating gate type thyristor is generally advantageous in that the steady-state loss is small. However, it is disadvantageous that it can not be turned-off, or has low controllable current even when it can be turned-off at high speed.
An emitter switched thyristor with a diverter (referred to as "ESTD" hereinafter) disclosed in Electron Device Letters, Vol. 16, (1995) is known as an example of an insulating gate type thyristor that has a turn-off capability and that is improved controllable current. FIGS. 63 and 64 show a sectional view and a plan view, respectively, of an ESTD. FIG. 63 is a cross sectional view taken along I--I of FIG. 64.
Referring to FIGS. 63 and 64, an ESTD includes a p.sup.+ anode 1, an n.sup.- layer 2, a p base 3, a p.sup.+ contact 4, an n.sup.+ cathode 5, a p diverter 6a, an n.sup.+ floating region 7a, gate oxide films 8a and 8b, gate electrodes 12a and 12b, an anode electrode 9, a cathode electrode 10, and a diverter electrode 11a. P.sup.+ anode 1, n.sup.- layer 2, p base 3, and n.sup.+ floating region 7a form a thyristor.
P base 3 and p.sup.+ diverter 6a form a p channel MOSFET by gate oxide film 8b. Cathode electrode 10 and diverter electrode 11a are electrically connected.
An operation of an ESTD will be described hereinafter. An on state is realized by applying a voltage higher than a threshold voltage to gate electrodes 12a and 12b while a forward bias is established between cathode electrode 10 and anode electrode 9, that is to say, in a state where cathode electrode 10 is grounded and a positive (+) voltage is applied to anode electrode 9.
More specifically, application of a voltage higher than a threshold voltage to gate electrodes 12a and 12b causes an n channel region of high electron density to be generated in a region of p base 3 sandwiched by n.sup.+ cathode 5 and n.sup.+ floating region 7a in the proximity of gate oxide film 8a. Also, an n channel region of high electron density is generated in a region of p base 3 sandwiched by n.sup.+ floating region 7a and n.sup.- layer 2 of a semiconductor substrate in the proximity of gate oxide film 8b. Electrons flow to the n channel region to be injected from cathode electrode 10 into n.sup.- layer 2 of the semiconductor substrate via n.sup.+ cathode 5 and n.sup.+ floating region 7a. Electrons flow towards p.sup.+ anode 1 to which a positive (+) voltage is applied. When the electrons arrive at p.sup.+ anode 1, holes are injected into n.sup.- layer 2 from p.sup.+ anode 1. Some of the holes injected into n.sup.- layer 2 flow into p base 3 to be conducted below n.sup.+ floating region 7a and n.sup.+ cathode 5 to enter p.sup.+ contact 4. Then, holes flow from p.sup.+ contact 4 towards cathode electrode 10.
When the holes stored within p base 3 become greater than the internal potential of the pn junction formed by n.sup.+ floating region 7a and p base 3, the holes will flow from p base 3 towards n.sup.+ floating region 7a to turn on the thyristor to initiate a thyristor operation. Thus, a main current flows across cathode electrode 10 and anode electrode 9. Here, the minimum current required for the turned-on thyristor to maintain its state is referred to as "holding current".
In contrast, an off-state is realized by applying a voltage lower than a threshold voltage to gate electrodes 12a and 12b. This operation will be described in detail hereinafter.
When a voltage lower than a threshold voltage is applied to gate electrodes 12a and 12b, the n channel region formed at p base 3 region sandwiched by n.sup.+ cathode 5 and n.sup.+ floating region 7a in the proximity of gate oxide film 8a, and also the n channel region formed at p base 3 region sandwiched by n.sup.+ floating region 7a and n.sup.- layer 2 of the semiconductor substrate in the proximity of gate oxide film 8b and are eliminated, whereby injection of electrons from cathode electrode 10 is suppressed.
Channel inversion occurs in the region of n.sup.- layer 2 of the semiconductor substrate sandwiched by p base 3 and p.sup.+ diverter 6a in the proximity of gate oxide film 8b. As a result, a p channel region of high hole density is generated. Since additional injection of electrons is not carried out, newly generation of holes is also not seen. The holes in p base 3 region will flow from p.sup.+ contact 4 towards cathode electrode 10. Furthermore, holes will flow towards p.sup.+ diverter 6a via the p channel region in the proximity of gate oxide film 8b. More specifically, the holes stored in p base region 3 will be diverted towards p.sup.+ diverter 6a.
When the hole-current flows towards cathode electrode 10 and diverter electrode 11a so that the main current becomes lower than the holding current level, the operation of the thyristor is inhibited since the thyristor cannot maintain its on-state. Thus, the main current across cathode electrode 10 and anode electrode 9 is cut off.
An emitter switched thyristor (referred to as "EST" hereinafter) is set forth in the following for the sake of describing the controllable current of a thyristor.
A plan view of an EST indicates a striped structure similar to that of FIG. 64. Referring to FIG. 65 showing a sectional view of EST, the structure of EST is identical to that of the ESTD provided that the p.sup.+ diverter and the diverter electrode are removed.
The operation of an EST is similar to that of an ESTD. However, holes stored in p base 3 region flow only towards cathode electrode 10 in the transition to an off-state. Therefore, a turn-off state is not easily achieved since the potential in p base 3 is higher than that in an ESTD. This means that the value of the maximum main current that can be turned off is lower than that for an ESTD. When the same main current is to be turned off, the time to attain a turn-off state becomes longer since there is no diversion towards the p.sup.+ diverter in comparison with an ESTD. It is said that the characteristics of an element is superior and that the controllable current is high as the value of the maximum main current that can be turned off is greater. The characteristic can be improved as the turn-off loss is reduced in proportion to a shorter turn-off time. It is therefore important to lower the potential of P base 3 to quickly draw out holes to improve the characteristics of a thyristor. A p.sup.+ diverter has a critical function for this purpose.
A base resistance thyristor (referred to as "BRT" hereinafter) disclosed in Electron Device Letters, Vol. 12 (1991) will be described hereinafter as another thyristor with such a p.sup.+ diverter.
FIGS. 66 and 67 show a sectional view and a plan view, respectively, of a BRT. FIG. 66 is a cross sectional view taken along I--I of FIG. 67.
Referring to FIGS. 66 and 67, a BRT includes a p.sup.+ anode 1, an n.sup.- layer 2, a p base 3, an n.sup.+ cathode 5, a p.sup.+ diverter 6a, a gate oxide film 8b, an anode electrode 9, a cathode electrode 10, and a diverter electrode 11a. A thyristor is formed by p.sup.+ anode 1, n.sup.- layer 2, p base 3, and n.sup.+ cathode 5.
An operation of a BRT will be described hereinafter. An on-state is realized by applying a voltage higher than a threshold voltage to gate electrode 12b. By applying the voltage to gate electrode 12b, an n channel region is formed in the region of p base 3 sandwiched by n.sup.+ cathode 5 and n.sup.- layer 2 of a semiconductor substrate in the proximity of gate oxide film 8b. Electrons are injected from cathode electrode 10 towards n.sup.- layer 2 of the semiconductor substrate through n.sup.+ cathode 5 and the n channel region. Holes are injected from p.sup.+ anode 1 towards n.sup.- layer 2. Here, holes are stored inside p base 3 to cause the potential to exceed the internal potential of the pn junction formed of n.sup.+ cathode 5 and p base 3. Holes flow from p base 3 towards n.sup.+ cathode 5 to initiate an operation of the thyristor by being turned on. Thus, a state is obtained in which a main current flows across cathode electrode 10 and anode electrode 9.
An off-state is realized by applying a voltage lower than a threshold voltage to gate electrode 12b.
When the voltage is applied to gate electrode 12b, the n channel region formed in the region of p base 3 sandwiched by n.sup.+ cathode 5 and n.sup.- layer 2 of the semiconductor substrate in the proximity of gate oxide film 8b is eliminated, whereby injection of electrons from cathode electrode 10 is ceased. Channel inversion occurs in the region of n.sup.- layer 2 of the semiconductor substrate sandwiched by p base 3 and p.sup.+ diverter 6a in the proximity of gate oxide film 8b to generate a p channel region of high hole density. The holes flowing through p base 3 are conducted towards p.sup.+ diverter 6a via the p channel region. Thus, a thyristor operation is suppressed when the current becomes lower than the holding current of the thyristor to cut off the main current.
In this BRT, holes flow through p diverter 6a in the transition to an off-state. Therefore, there is an effect similar to that of reduction in the resistance of p base 3 of the thyristor formed of p.sup.+ anode 1, n.sup.- layer 2, p base 3, and n.sup.+ cathode 5. Thus, the controllable current is improved when the thyristor is turned off, that is, when the effective holding current is increased during channel inversion.
As described above, an insulating gate type thyristor including a p.sup.+ diverter has the holes stored in the p base also conducted towards the p.sup.+ diverter when turned off to be increased in controllable current in comparison to a thyristor does not include a p.sup.+ diverter.
It is appreciated from FIGS. 64 and 67 that a p diverter has a plane structure of stripes. When a higher current is to be cut off at high speed, the current diverting efficiency of the hole-current is degraded since there is only one p.sup.+ diverter region. It was difficult to improve the controllable current for high currents. Since the flow of the hole-current is gathered towards one p.sup.+ diverter in the split of the current, there are cases where the thyristor operates erroneously.
It is to be noted that the p.sup.+ diverter region in an ESTD or a BRT is in direct contact with n.sup.- layer 2 as shown in FIGS. 63 or 66. Therefore, a portion of the current flows also towards the p.sup.+ diverter 6a from the p.sup.+ anode 1 in an on-state. There was a problem of turn-on loss which is the power loss generated when the thyristor is turned on to compensate for the current flowing towards p.sup.+ diverter 6a. There was also a steady-state loss generated by the on-state resistance in a steady state after being turned on. In other words, there was a problem of increase in power loss represented by the product of the on-state voltage and the main current.